Power optimization in configurable ALU using blend of techniques

Project Code :TVPGFE330

Objective

The main objective of this project is to reduce the power dissipation for the design of ALU using different configurations of Clock gating Technique.

Abstract

Reduction in power dissipation is an essential design issue in VLSI circuit. One of the important block in any processor is Arithmetic Logic Unit and it performs arithmetic and logical operations. If operations are more and more complex then power dissipation is more. The clock network is a major source of power dissipation so we can reduce significant amount of power if we can gate the clock whenever it isn’t required. From the literature, we have noticed that there several methods/techniques used to reduce the power within ALU, the used methods are moderate and still there is scope to reduce power using blend of techniques. So low power ALU is designed using clock gating techniques besides using PIPO and Booth’s algorithm concept. By giving specific opcode, we can enable the specific operation and other operations are in inactive mode, so we can see less power dissipation in ALU. Low power ALU is having two 8 bit input data with cin, bin, enable and 2 bit shift data and a decoder 4:16 to select the 16 operations by giving 4 bit opcode to it as a input with start enable function. At each iteration the proposed design is implemented with one of these clock gating techniques i.e latch free clock gated technique, latch based clock gated technique, flip flop based clock gated technique, and synthesis based clock gating technique with parallel in parallel out (PIPO) shift registers. These all techniques are performed with operation selection feature and PIPO shift registers in this design at different operating frequencies 100MHZ, 200MHZ, 400MHZ, 500MHZ and 1GHZ in Virtex-6. Virtex-6 FPGA board having 40nm technology with 1 volt in Xilinx ISE 14.4 tool. This paper mainly focuses to analyse the dynamic power dissipation for various frequencies in ALU with and without clock gating techniques combining with PIPO and Booth’s algorithm methods

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

· Xilinx Vivado Tool

· HDL: Verilog

Hardware Requirements:

· Microsoft® Windows XP

· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support

· 512 MB RAM

· 100 MB of available disk space

Learning Outcomes

Understanding voltage level shifting: Gain knowledge about the concept of voltage level shifting and its importance in electronic systems. Learn about the challenges and considerations involved in converting voltage levels between different supply voltages.
Familiarity with dual-supply applications: Explore the specific requirements and characteristics of dual-supply applications. Understand why and when dual-supply configurations are used and the benefits they offer in certain scenarios.
Knowledge of existing voltage level shifting techniques: Study various existing techniques and approaches for voltage level shifting in dual-supply applications. Understand their advantages, limitations, and trade-offs in terms of speed, power efficiency, area utilization, and performance.
Analyzing the high-speed requirement: Gain insights into the need for high-speed voltage level shifters in certain applications. Understand the implications of high-speed requirements on power consumption, signal integrity, and overall system performance.
Investigating power efficiency: Explore the significance of power efficiency in voltage level shifting designs. Learn about low-power design techniques, such as power gating, supply voltage scaling, and optimizing circuit topologies, to achieve power-efficient operation.
Designing a high-speed and power-efficient voltage level shifter: Apply the knowledge gained to design a voltage level shifter that meets the requirements of high speed and power efficiency in dual-supply applications. Understand the design considerations, trade-offs, and challenges involved in achieving these objectives.
Simulation and analysis: Utilize simulation tools and techniques to validate the design, analyze its performance, and assess its speed and power efficiency. Gain hands-on experience in simulating and analyzing the behavior of voltage level shifters under different operating conditions.
Evaluating trade-offs: Develop the ability to evaluate trade-offs between speed, power efficiency, area utilization, and other performance metrics. Understand how design choices and optimization strategies impact these trade-offs and make informed decisions based on the specific requirements of the application.
Documentation and reporting: Develop effective communication skills by documenting the design process, results, and findings in a clear and concise manner. Prepare a comprehensive report summarizing the design, implementation, and performance analysis of the high-speed and power-efficient voltage level shifter.
Critical thinking and problem-solving: Enhance critical thinking and problem-solving skills by identifying and addressing challenges and limitations in the design process. Explore alternative solutions, evaluate their feasibility, and propose improvements or optimizations to enhance the speed and power efficiency of the voltage level shifter