Power Efficient Tiny Yolo CNN using Reduced Hardware Resources Based on Booth Multiplier and WALLACE Tree Adders

Also Available Domains Arithmetic Core|Xilinx Vivado|Xilinx ISE

Project Code :TVMAFE130

Objective

The objective of this project is to reduce the resources on FPGA consumed by CNN accelerators and improve the system performance in terms of power. For reducing the power, a new processing element based on MBE multiplier to replace MAC units and WALLACE tree adders as an alternate solution for deep binary adder trees is proposed

Abstract

The term Deep Learning or Deep Neural Network refers to Artificial Neural Networks (ANN) with multi layers. Over the last few decades, it has been considered to be one of the most powerful tools, and has become very popular in the literature as it is able to handle a huge amount of data. In CNN, processing elements plays a vital role for the accelerator design. To reduce the amount of hardware resources and power consumption, this project provides a new processing element design as an alternate solution for hardware implementation.

Modified Booth Encoding (MBE) multiplier and WALLACE tree-based adders are proposed to replace bulk MAC units and typical adder tree respectively. The synthesis and simulation are verified by using Xilinx ISE 14.7 version tool.

Keywords: Convolutional Neural Network, Booth Encoding Multiplier, WALLACE Tree Adders, Processing Elements

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