This paper describes the study of sample and hold circuit, comparator and encoder in 4-bit Flash Analog to Digital Converter (ADC) to get a power efficient ADC.
The interface between the crucial world analogue signal and therefore the digital signal processors is represented by analog-to-digital converters (ADCs), which are useful building blocks in various applications like a biomedical, data storage read channel, and an optical receiver. This work makes an effort to design a power-efficient 4-bit Flash Analogue to Digital Converter (ADC) for biomedical applications. Additionally, in order to create a 4-bit Flash Analogue to Digital Converter (ADC) that is power efficient, this paper discusses the study of the sample and hold circuit, comparator, and encoder. To lower power consumption, the typical comparator is substituted in this work with a sample and hold circuit instead of an R-2R ladder. The priority encoder is used as a replacement for the classic encoder and is simply replaced with a simple comparator. 0.18 m CMOS technology is used in its implementation. In most cases, the schematics and simulations are done using the CADENCE VIRTUOSO tools. The analogue input range at a certain frequency range is one of the outputs of the simulation.
Index Terms: Flash ADC, CADENCE VIRTUOSO, gpdk180, Resolution.
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Software Requirements:
Β· Tool: Cadence Virtuoso
Β· Technology : 0.18um CMOS technology
Minimum Hardware Requirements:
Β· Microsoft Windows 7
Β· Intel i3 processor or equivalent
Β· 4GB RAM
Β· 100MB of available disk space
LEARNING OUTCOMES:
o Data Flow modeling.
o Structural modeling.
o Behavioral modeling.
o Mixed level modeling.
Β· About approximation computing.
Β· Xilinx Vivado 2018.3/Xilinx ISE 14.7 Suite for design and simulation.
Β· Generation of Netlist.
Β· Solution providing for real time problems.
Β· Project Development Skills:
o Problem Analysis Skills.
o Problem Solving Skills.
o Logical Skills.
o Designing Skills.
o Testing Skills.
o Debugging Skills.
o Presentation Skills.
o Thesis Writing Skills.