Power-Area Optimized Multiplier Design using In-Memory Computation

The von Neumann bottleneck arising from frequent data transfers between processor and memory has become a critical limitation in modern computing systems, particularly for data-intensive applications. In-Memory Computation (IMC) offers a promising paradigm to address this challenge by performing arithmetic operations directly within the memory array, eliminating excessive data movement. This paper presents a power-area optimized multiplier design exploiting in-memory computation techniques. The proposed multiplier leverages SRAM-based computation structures to perform multiplication using bitwise logical operations within the memory cells. The architecture is designed and evaluated using standard CMOS technology. Experimental results demonstrate significant improvements in power consumption and area footprint compared to conventional CMOS multiplier designs, making it well-suited for AI accelerators, edge computing, and energy-constrained DSP applications.

Keywords: In-Memory Computing, Multiplier, Low Power, Area Optimization, Processing-in-Memory, SRAM, CMOS, Edge Computing