Power and Area Optimized Data Path Unit for A RISCV Processor

The primary objective of “Power and Area Optimized Data Path Unit for A RISC-V Processor” is to design and implement a data path architecture for a RISC-V processor that minimizes both silicon area and power consumption without significantly degrading performance. This work focuses on optimizing the internal data path components — such as the ALU, register file, and pipeline interconnections — to achieve an efficient balance between energy efficiency and hardware resource usage. By leveraging microarchitectural techniques (e.g., narrowed datapaths, hardware sharing, and simplified control logic), the design aims to reduce dynamic switching and static leakage, making it suitable for resource-constrained embedded and IoT applications that require low power yet effective computational capability.