Power and area efficient FIR filter architecture in digital encephalography systems

Also Available Domains DSP Core

Project Code :TVMAFE790

Objective

The proposed method focuses on applying FIR filters to denoise noisy images, with the FPGA platform serving as the hardware implementation for efficient processing. The design of the FIR filter is optimized for FPGA architecture, allowing for high-speed processing of image data.

Abstract

In this paper, we present an FPGA-based approach for the analysis and performance evaluation of Finite Impulse Response (FIR) filters applied to noise reduction in image processing. FIR filters are widely used for signal and image processing due to their inherent stability and ease of implementation. The proposed method focuses on applying FIR filters to denoise noisy images, with the FPGA platform serving as the hardware implementation for efficient processing. The design of the FIR filter is optimized for FPGA architecture, allowing for high-speed processing of image data. A noise image, generated using Gaussian noise, serves as the input to the system. The paper evaluates the performance of various FIR filter configurations, analyzing their effectiveness in reducing noise while preserving image details. The results demonstrate the superior performance of FPGA-based FIR filters in terms of processing speed and noise reduction when compared to traditional software implementations. This study highlights the potential of FPGA-based FIR filter designs in real-time image processing applications, including medical imaging, satellite imagery, and video surveillance systems, where both high performance and low latency are crucial.The synthesis and simulation of the proposed designs can be implemented using Xilinx Vivado 2018.3.

Key words: bilateral filtering, FPGA-based designs, image denoising

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

SPECIFICATIONS

Software Requirements:

· Xilinx Vivado2018.3HDL: Verilog and matlab 2020a

Learning Outcomes

The use of Verilog for FIR filter design has several advantages, particularly when implemented on FPGA platforms. First, FPGA hardware is inherently parallel, meaning that multiple pixel operations can be performed simultaneously. This results in faster processing speeds, making it ideal for applications where speed is critical. Second, FPGAs can be customized to meet the specific needs of the application, allowing for optimization of the filter design to improve both speed and efficiency. Finally, because the FIR filter is implemented in hardware, it reduces the computational burden on the CPU, allowing for faster processing of images without relying on software-based filters, which can be slower and less efficient

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Front End Domains

Arithmetic Core
Communications
DSP Core
FPGA

Back End Domains

Core Memories
Low Power VLSI
Transistor Logic
Nano Technology

Tools

Xilinx ISE
FPGA
Cadence EDA
Xilinx Vivado

Others

Matlab Interfacing