Performance Evaluation of 6T-Sram in Sub-3 nm Complementary Fet

This work presents a comprehensive performance evaluation of a 6-transistor (6T) SRAM cell implemented using sub-3 nm Complementary Field-Effect Transistor (CFET) technology. As traditional CMOS and FinFET scaling approaches its physical and electrostatic limits, CFET emerges as a promising device architecture by vertically stacking nMOS and pMOS transistors to achieve higher density and superior gate control.

In this work, a conventional 6T SRAM topology is adapted to CFET-based devices and analyzed under ultra-scaled conditions. Key performance metrics such as static noise margin (SNM), read stability, write ability, leakage power, and access delay are evaluated. The design aims to address major scaling challenges including increased leakage, reduced noise margins, and variability effects.

Simulation results demonstrate that the CFET-based SRAM cell achieves improved area efficiency, reduced leakage power, and enhanced electrostatic control compared to conventional FinFET-based SRAM designs, while maintaining reliable read and write operations. The proposed approach is well-suited for next-generation high-density, low-power memory applications in advanced VLSI systems.

Keywords

6T SRAM, CFET, Sub-3 nm Technology, Static Noise Margin (SNM), Low Power, Advanced VLSI, Memory Design