Performance Comparison of 16-Bit ALU and 32-Bit ALU Using Verilog

The increasing demand for efficient and high-performance embedded systems drives the need for optimized Arithmetic and Logic Units (ALUs), which are fundamental to their operation. This study aims to address the trade-offs in area, propagation delay, and power consumption, ensuring balanced performance for diverse applications. The study compares the performance of 16-bit and 32-bit ALUs, focusing on key metrics such as area, propagation delay, and power consumption. A trade-off between area and power dissipation is observed, with the 32-bit ALU consuming more power and occupying more area than the 16-bit ALU. To ensure low power consumption, the design activates only one operation and circuit set at a time. The Artix7 FPGA board is utilized to evaluate and compare the performance, with simulations conducted using Verilog and the Xilinx vivado software tool. This study presents the design and analysis of a 16-bit Register Transfer Level (RTL) ALU, showcasing its architectural efficiency with reduced complexity through functional blocks such as adders, subtractors, and logic gates. Synthesis results demonstrate optimized technology schematics using Xilinx specific components, LUTs and carry logic, ensuring enhanced performance and early issue detection. 

Keywords—ALU, power consumption, propagation delay and area.