The demand for high speed processing has been increasing as a result of expanding computer and signal processing applications. One of the key arithmetic operations in such applications is multiplication and the development of fast multiplier circuit has been a subject of interest over decades. Reducing the time delay and power consumption are very essential requirements for many applications. Multiplier based on Vedic Mathematics is one of the fast and low power multiplier. In Vedic multipliers there are two types of techniques for multiplications based on UrdhvaTriyagbhyam and Nikhilam sutras, each offering different advantages and having tradeoff in terms of speed, circuit complexity, area and power consumption. In this paper the comparison of these architectures is carried out to know the best architecture for multiplication with respect to power and delay characteristics. The design of architectures is done in Verilog HDL and the tool used for simulation is Xilinx 14.3 ISE.