Performance Analysis of SRAM Cell Designed using MOS and Floating-gate MOS for Ultralow Power Technology

In modern VLSI systems, Static Random Access Memory (SRAM) plays a crucial role as a primary storage element, directly influencing the performance, power efficiency, and reliability of integrated circuits. Conventional SRAM cells designed using MOS transistors face challenges such as increased leakage current, higher standby power, and scaling limitations in advanced technology nodes. To address these issues, Floating-Gate MOS (FGMOS) devices have emerged as a promising alternative due to their ability to achieve programmable threshold voltages, reduced leakage paths, and improved charge retention characteristics. This work presents a comparative performance analysis of SRAM cells designed using conventional MOSFETs and FGMOS devices for ultralow-power technology applications. The study focuses on key design parameters including power consumption, static noise margin (SNM), delay, and area efficiency. Simulation results demonstrate that FGMOS-based SRAM cells significantly reduce leakage power while maintaining stable read/write operations, thereby enhancing energy efficiency without compromising reliability. The proposed approach highlights the potential of FGMOS-based SRAM design as a viable solution for next-generation low-power memory architectures, particularly in applications such as IoT devices, biomedical implants, and portable electronics.