Performance Analysis of 8-bit, 16-bit, 32-bit and 64-bit ALUs with CMOS-Based Reversible Gates Using Advanced Power Reduction Techniques

This work presents a comparative analysis of multi-bit ALU architectures designed using CMOS-based reversible logic gates combined with advanced power-reduction techniques. Conventional CMOS ALUs suffer from information loss and heat generation, whereas reversible logic enables low-energy computation by ensuring one-to-one mapping between inputs and outputs. In this study, scalable ALUs of different word sizes are implemented by cascading optimized reversible full-adder and control-logic blocks. Power-saving methods such as minimized garbage outputs, reduced constant inputs, optimized transistor-level reversible gates, and leakage-aware switching strategies are used to enhance efficiency. Performance is evaluated in terms of area, delay, switching activity, and total power consumption across 8-bit, 16-bit, 32-bit, and 64-bit architectures. The results indicate a consistent improvement in energy behaviour as reversible gates significantly reduce computation losses, demonstrating their effectiveness for low-power arithmetic units in modern VLSI and quantum-ready designs.

Index Terms: Reversible logic, ALU (Arithmetic and Logic Unit), power dissipation, garbage output, COG gate, HNG gate.