Performance Analysis of 4-Bit Multiplier using 90nm Technology

This research investigates the performance of three distinct 4-bit multipliers constructed using a modified full adder at the 90nm technology node. The study focuses on comparing the efficiency of low-power, high-speed multiplier designs against their CMOS counterparts. Given the substantial power consumption and impact on circuit speed associated with the multiplier module, the proposed multipliers aim to optimize and enhance overall circuit performance. Analyzing the results of our study, we observe that the proposed multipliers offer significant advantages over CMOS-based designs, including up to approximately power reduction, decrease in delay, and approximately   decrease in transistor count, increase in speed by using 90nm technology