Parallel Implementation Of Model Predictive Control For Multilevel Cascaded H-bridge Statcom With Linear Complexity

This project presents a parallel implementation approach to reduce the execution time of model predictive control (MPC) for cascaded H-bridge static synchronous compensators(STATCOMs), where the field programmable gate array (FPGA) is configured to be used for  accelerating the high-complexity sorting tasks. By running the digital signal processor (DSP) and FPGA in parallel, the algorithm execution time is only determined by the DSP, and the resource consumption is only determined by the FPGA. To minimize the resource consumption and requirement in FPGA, a parallel comparison-based sorter with multiple comparison and accumulators is proposed. The proposed implementation method can reduce the time and space  complexity of the MPC from the polynomial level to a linear level without additional hardware cost, which means the MPC for medium-voltage cascaded H-bridge STATCOMs (e.g. 20 stages) can be implemented online with existing control platforms.