Optimizing High-Level Synthesis Sparse Matrix-Vector Kernel for Alveo FPGAs

Sparse matrix-vector multiplication (SpMV) is a critical kernel in scientific computing and high-performance applications, yet it remains challenging to optimize due to irregular memory access patterns and low computational intensity. This work targets the AMD Vitis SpMV kernel on HBM-equipped Alveo FPGAs and introduces hardware-aware optimizations that significantly improve performance, especially in reduced precision scenarios. Building on prior evaluations of the Vitis kernel, we propose two key enhancements: coefficient grouping and index packet coalescing. These reduce padding overhead and improve memory bandwidth efficiency without requiring a complete redesign of the vendor-supplied kernel. Experimental results over 33 matrices from the SuiteSparse collection show up to 4× speedup and an average improvement of 1.6× compared to the original Vitis kernel. Our method demonstrates how practical architectural adaptations can yield substantial performance gains, supporting the growing trend toward lower-precision and energy-efficient computing in FPGA-based accelerators.