Optimizing Ternary Multiplier Design with Fast Ternary Adder

Also Available Domains Low Power VLSI|Cadence EDA

Project Code :TVMATO1072

Objective

The main objective of this paper is to design the ternary multiplier using ternary adders in order to minimize the power consumption.

Abstract

In this paper, ternary Wallace tree multipliers that reduce the number of transistors by using 4-input ternary adders are proposed to improve the performance of existing ternary multipliers. A ternary carry-select adder is also proposed to reduce the carry propagation delay, used as a carry-chain adder of the Wallace tree. The proposed multipliers are designed with a custom ternary standard cell library synthesized by multi-threshold complementary metal-oxide-semiconductor (CMOS) with a 45 nm process. Power and delay are verified via HSPICE simulation

KEYWORDS: Multi-valued logic, ternary logic circuit, ternary multiplier, Wallace tree, ternary adder

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

· H-spice

· Technology files: 45nm

Hardware Requirements:

· Microsoft® Windows XP

· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support

· 512 MB RAM

· 100 MB of available disk space

Learning Outcomes

Introduction to adders

Types of Adders
Limitations & Applications
Basics of Ternary Adder

Knowledge on Multiplier
Transistors & its applications

o Types of Transistors

o Logic Gates using Transistors

o Pull Up and Pull-Down networks

o Importance of Transistors

· MOS Fundamentals

· NMOS/PMOS/CMOS Technologies

· How to design circuits using Transistor logic?

· How to design low power, high speed area efficient transistor level circuits?

· Introduction to Analog Electronics

· Importance of ternary Wallace tree multipliers.

· Applications in real time

H-spice tool for design and simulation
Solution providing for real time problems

· Project Development Skills:

o Problem Analysis Skills

o Problem Solving Skills

o Logical Skills

o Designing Skills

o Testing Skills

o Debugging Skills

o Presentation skills

o Thesis Writing Skills

Demo Video

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Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice