Optimizing FPGA Logic Block Architectures for Arithmetic
Also Available Domains Arithmetic Core|Xilinx ISE
Objective
The main objective of this paper is to reduce the power in field-programmable gate arrays (FPGAs) to improve the efficiency of arithmetic functions. In this paper, we are designing the 1-bit full adder and 4-bit CLA with the different LUT structures in FPGAs
Abstract
In this project, we studied on different FLUT architectures which are used in FPGAs. Hardened adder and carry logic is widely used in commercial field-programmable gate arrays (FPGAs) to improve the efficiency of arithmetic functions.
There are many design choices and complexities associated with such hardening, including circuit design, FPGA architectural choices, and the Computer Aided Design (CAD) flow. However, these choices have not been studied much and hence we explore a number of possibilities. We show that hard adders and carry chains increase the performance of simple adders by a factor of 4 or more.
Our best non-fracturable lookup table (non-FLUT) architecture with hardened arithmetic yields better area–delay product than architectures without hardened arithmetic. The effectiveness of the proposed method is synthesized and simulated using Xilinx Vivado.
Keywords: Field Programmable Gate Arrays (FPGAs), logic design, Fracturable Look Up Table
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Block Diagram
Specifications
Software Requirements:
- Xilinx Vivado
- HDL: Verilog
Hardware Requirements:
- Microsoft® Windows XP
- Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
- 512 MB RAM
- 100 MB of available disk space
Learning Outcomes
- Basics of Digital Electronics
- FPGA design Flow
- Introduction to Verilog Coding
- Different modeling styles in Verilog
- Data Flow modeling
- Structural modeling
- Behavioral modeling
- Mixed level modeling
- Combinational & Sequential circuits
- Knowledge on Arithmetic circuits
- Ripple Carry Adder
- Carry Look Ahead Adder
- About Look Up Table
- Non Fracturable Lookup Table
- Fracturable Lookup Table
- Basic Logic Elements
- Knowledge on CAD Flow
- Applications in real time
- Xilinx Vivado for design and simulation
- Generation of Netlist
- Solution providing for real time problems
- Project Development Skills:
- Problem Analysis Skills
- Problem Solving Skills
- Logical Skills
- Designing Skills
- Testing Skills
- Debugging Skills
- Presentation Skills
- Thesis Writing Skills
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