Optimized Reversible Multiplier Circuit

In this we present a reversible logic gates based multiplier. Reversible logic circuits have received significant attention in nanotechnology. This paper presents two new 4×4 bit reversible multiplier designs which have lower hardware complexity, less garbage bits, less quantum cost and less constant inputs than previous ones, and can be generalized to construct efficient reversible n×n bit multipliers. An implementation of reversible HNG is also presented. This implementation shows that the full adder design using HNG is one of the best designs in term of quantum cost. In the proposed method of multiplier we are implementing 2 multipliers with HNG full and Peres full adder. By this we can get the less hardware complexity and number logic gates used in proposed methodology is reduced. The synthesis and simulation are verified by using Xilinx ISE 14.7 version tool.