Optimized High Speed Radix-8 FFT algorithm implementation on FPGA

Also Available Domains Xilinx Vivado|Xilinx ISE

Project Code :TVMAFE441

Abstract

In this project, we will be implementing 8, 16 point DIF FFT using Radix 2 and modified Radix 8 are designed and implemented. The Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (IFFT) involves butterfly Radix methodology for conversion. A new algorithm is implemented by the reorientation of the computation of Radix-8, which in turn reduces the complex multiplication operation. In the recent years, the processing unit in receiving are time, power and area consuming, optimization is the key factor that can improve the performance of the design. Time domain to frequency domain conversation is the highest priority operation in the receiving end of the communication channel. Radix-8 FFT has provided convincing result which is implemented, the latency, area and power consumption is reduced significantly.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

Xilinx Vivado 2018.3 Tool
HDL: Verilog

Hardware Requirements:

Microsoft® Windows XP
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

Basics of Digital Electronics
VLSI design Flow
Introduction to Verilog Coding
Different modeling styles in Verilog

Data Flow modeling
Structural modeling
Behavioral modeling
Mixed level modeling

Introduction to Fourier transform
Knowledge on Fourier series
Different types of signals
Knowledge on Radix-r butterfly units
Knowledge on DFT, FFT
Applications in real time
Xilinx ISE 14.7/Xilinx Vivado for design and simulation
Generation of Netlist
Solution providing for real time problems
Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation Skills
Thesis Writing Skills

Demo Video

Request Video

Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice