Novel Binary Signed-Digit Addition Algorithm for FPGA Implementation
Also Available Domains Xilinx Vivado
Objective
In this project, we are going to design a new signed-digit (SD) carry-free addition algorithm to show that the speed of addition is faster than the conventional signed-digit (SD) adder.
Abstract
In this project, we are going to design a new signed-digit (SD) carry-free addition algorithm to show that the speed of addition is faster than the conventional signed-digit (SD) adder. Addition is one of the most important arithmetic operations in digital computation. Optimization of adders speed, power, and area is a challenging task. High performance addition and addition related operations, such as multiplication, play an important role in the computer-based computational paradigm. A major impediment to improving the speed of arithmetic execution units incorporating addition and addition related operations is the presence of carry and borrow chains. Signed-digit (SD) number representation systems have been studied for high-speed arithmetic. One important property of the SD number system is the possibility of performing addition without long carry chain. However, many numbers of logic elements are required when the number representation system and such an adder are realized on a logic circuit. In this study, we propose a new adder on the binary SD number system called novel SD addition algorithm. This algorithm is based on the adder of an SD represented number together with a binary represented number. The main difference between the conventional algorithm and proposed one is the calculation rules of intermediate sums and carries. The conventional algorithm uses lower digits for obtaining the intermediate sum and carry. Conversely, the proposed one does not use these digits. The synthesis and simulation of the proposed designs can be implemented using Xilinx Vivado2018.3/Xilinx ISE 14.7Suite.
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Block Diagram
Specifications
Specifications:
Software Requirements:
· Xilinx Vivado 2018.3 Tool.
· HDL: Verilog.
Hardware Requirements:
· Microsoft® Windows XP.
· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support.
· 512 MB RAM.
· 100 MB of available disk space.
Learning Outcomes
Learning Outcomes:
- Basics of Digital Electronics.
- Concept of binary addition
- Difference between signed and unsigned binary addition
- Introduction to Verilog Coding.
- Different modeling styles in Verilog.
o Data Flow modeling.
o Structural modeling.
o Behavioral modeling.
o Mixed level modeling.
- Introduction to adder design.
- About signed digit addition.
- Knowledge on intermediate sum and carry generation.
- Knowledge on adders.
- About approximation computing.
- Applications in real time.
· Xilinx Vivado 2018.3/Xilinx ISE 14.7 Suite for design and simulation.
· Generation of Netlist.
· Solution providing for real time problems.
· Project Development Skills:
o Problem Analysis Skills.
o Problem Solving Skills.
o Logical Skills.
o Designing Skills.
o Testing Skills.
o Debugging Skills.
o Presentation Skills.
o Thesis Writing Skills.
Paper Publishing
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