New Majority Gate Based Parallel BCD Adder Designs for Quantum-Dot Cellular Automata

In this paper, we first theoretically re-defined output decimal carry in terms of majority gates and proposed a carry look ahead structure for calculating all the intermediate output carries. We have used this method for designing the multi-digit decimal adders. Theoretically, our best n-digit decimal adder design reduces the delay and area-delay product (ADP) by 50% compared with previous designs. We have implemented our designs using QCADesigner tool. The proposed QCADesigner based 8-digit PBA-BCD adder achieves over 38% less delay compared with the best existing designs.