New Majority Gate Based Parallel BCD Adder Designs for Quantum-Dot Cellular Automata

We used this method to design the decimal multi-digit adders. In this paper, we first carried out the terms of majority gates theoretically by redefined output decimals and then proposed a carry lookahead structure to calculate all the carriers of intermediate output. The n-digit decimal adder design potentially decreases the delay and area delay product (ADP) when compared to previous models. We used the QCA Designer tool to execute our designs. The proposed adder based on QCA Designer which achieves less delay than the best existing designs.