Multistage Linear Feedback Shift Register Counters with Reduced Decoding Logic in 130-nm CMOS for Large-Scale Array Applications

Also Available Domains Xilinx Vivado|Xilinx ISE

Project Code :TVMAFE126

Objective

The main aim of this work is to improve performance in Multi stage Linear Feedback Shift Register by using new counter design and decoding logic scheme.

Abstract

The binary counters occupy having a lot of area and performance to beat this disadvantage we will use linear feedback shift register (LFSR) counters. The LFSR counters compatible for applications requiring large arrays of counters and that we will improve the performance and area. To decode the count order into binary we tend to needed significant logic, causing system on chip designs to be unfeasible. The multi stage LFSR counters having same benefits of single stage LFSR counter only needs decoding logic that scales logarithmically with the number of stages instead of exponentially with the number of bits as required by different methods. The effectiveness of the proposed method is synthesized and simulated using Xilinx ISE 14.7

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Block Diagram

Specifications

Software Requirements:

Xilinx ISE Tool
HDL: Verilog

Hardware Requirements:

Microsoft® Windows XP,
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

Basics of Digital Electronics
FPGA design Flow
Introduction to Verilog Coding
Different modeling styles in Verilog

Data Flow modeling
Structural modeling
Behavioral modeling
Mixed level modeling

Combinational & Sequential circuits
Knowledge on Arithmetic circuits
About Multi-stage LFSR
Study on Decoding logic and ripple carry logic
Applications of multi-stage LFSR in real time
Xilinx ISE 14.7 for design and simulation
Generation of Netlist
Solution providing for real time problems
Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation Skills
Thesis Writing Skills

Demo Video

Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice