Modulation For The Avc-heric Inverter To Compensate For Deadtime And Minimum Pulse Width Limitation Distortions

Modulation for the AVC-HERIC Inverter to Compensate for Deadtime and Minimum Pulse Width Limitation Distortions.

Abstract

            With the superiority in leakage current suppression, the active voltage clamping highly efficient and reliable inverter concept (AVC-HERIC) has become a promising candidate in low- and medium-power PV systems. In addition, the high power density and low system costs have been attained in the AVCHERIC due to the removal of the isolation transformers. However, to maintain high efficiency and good power quality under reactive power injection, prior-art modulation methods for the AVC-HERIC should be modified. In this paper, a simple modulation scheme is proposed for the AVC-HERIC, which ensures bidirectional current flow at any time. An improved modulation scheme is implemented according to the reference voltage polarity, and it is integrated into the proposed scheme to enable flexible reactive power injection. Moreover, the improved modulation scheme can maintain the same high efficiency as adopting the unipolar pulse width modulation (UP-PWM) strategy. More importantly, the deadtime and minimum pulse width limi ation (MPWL) distortions are compensated effectively by the proposed modulation, leading to a good power quality..