Memristor-Based Power Efficient 4T3M SRAM Cell

Random Access Memory (RAM) cells are fundamental components in modern electronic systems, especially within portable and embedded applications. Static Random Access Memory (SRAM), in particular, is preferred for its high speed and simple architecture. However, one of the main challenges in designing SRAM cells lies in minimizing power consumption—a critical requirement in ultra-low-power domains such as implantable biomedical devices. A common strategy for reducing power in CMOS-based SRAM involves lowering the supply voltage; however, this also compromises read/write stability due to increased susceptibility to process variations.

To address these limitations, this study presents a novel SRAM architecture that integrates memristor technology with conventional SRAM cells. The inclusion of memristors not only reduces transistor count and propagation delay but also significantly lowers overall power consumption while maintaining high stability. The proposed 4T3M (4-transistor, 3-memristor) hybrid SRAM design was thoroughly analyzed for key performance parameters such as Static Noise Margin (SNM), delay, and power usage, using 65nm CMOS technology in Cadence Virtuoso.

Simulation results demonstrate that the proposed architecture achieves nearly a threefold reduction in power consumption compared to existing memristor-based SRAM designs. To the best of the authors’ knowledge, this specific 4T3M hybrid configuration has not been reported in the literature to date.

Building upon this architecture, we further propose the implementation of a high-speed, low-power array multiplier using the combined advantages of SRAM and memristor devices. This hybrid approach utilizes the non-volatility and compact footprint of memristors, along with the rapid data access of SRAM, to deliver enhanced computational speed, reduced delay, lower transistor overhead, and improved energy efficiency—making it ideal for arithmetic processing in low-power VLSI applications.

Keywords: Memristor, SRAM, Low Power Memory, 4T3M Architecture, Array Multiplier, Biomedical De