MapReduce Model Using FPGA Acceleration for Chromosome Y Sequence Mapping

Also Available Domains DSP Core|Xilinx Vivado

Project Code :TVMATO769

Abstract

In this project, Divide and conquer based DNA sequencing algorithm has been proposed. Sequence alignment is the foundation of bioinformatics by a computational search through large genome sequence databases, which generally requires enormous amounts of memory and takes a long execution time. In this paper, an Optimized Smith-Waterman algorithm based on the Gotoh algorithm with an affine gap for accuracy alignment, the divide and conquer technique, and the MapReduce framework implemented to establish a parallel process. This model was implemented on Virtex 7 field programmable gate arrays (FPGAs). These techniques provide a better performance, reduce the hardware requirements, improve the accuracy, increase the computational throughput, and accelerate the alignment process for big data available in a complete Y chromosome. The hardware proposed system can achieve high performance, low time consumption 1.699 ns, and decrease FPGA utilization for big data alignments Y chromosome is used as an example.

Keywords:-. MapReduce, PHSW-DC, Gotoh, smith-waterman, Y chromosome.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

  • Xilinx ISE Tool 
  • HDL: Verilog

Hardware Requirements:

  • Microsoft® Windows XP,
  • Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support 
  • 512 MB RAM
  • 100 MB of available disk space

Learning Outcomes

  • Basics of Digital Electronics
  • VLSI design Flow
  • Introduction to Verilog Coding
  • Different modeling styles in Verilog
    • Data Flow modeling
    • Structural modeling
    • Behavioral modeling
    • Mixed level modeling
  • Introduction to sequence mapping circuits
  • Knowledge on types of DNA nucleotides
  • Different sequence mapping algorithms
  • Knowledge on smith waterman algorithm
  • Applications in real time
  • Xilinx ISE 14.7 for design and simulation
  • Generation of Netlist
  • Solution providing for real time problems
  • Project Development Skills:
    • Problem Analysis Skills
    • Problem Solving Skills
    • Logical Skills
    • Designing Skills
    • Testing Skills
    • Debugging Skills
    • Presentation Skills
    • Thesis Writing Skills


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