Low Voltage and Low Power 64-Bit Hybrid Adder Design Based on Radix-4 Prefix Tree Structure
Also Available Domains Arithmetic Core|Xilinx ISE
Objective
the proposed 64-bit hybrid adder is superior to other referenced adders, and has 203 ps delay time, 9.58 mw average power, and 96×76 [1]m2 area.
Abstract
Abstract:
A 64-bit hybrid adder design is proposed by using both radix-4 prefix tree structure and carry select adder for low voltage and low power applications. In order to optimize the features of this adder, some design issues are concerned including optimal layout for CMOS group generate/propagate circuit to reduce area, design of carry bypass adder (CBA) without conflict to boost speed, carry select adder (CSA) design with speed and area efficiency, and so on. Based on TSMC 90 nm CMOS mixed signal process technology at 1V supply voltage, the experimental results reveal that the proposed 64-bit hybrid adder is superior to other referenced adders, and has 203 ps delay time, 9.58 mw average power, and 96×76 [1]m2 area.
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Block Diagram
Specifications
Specifications:
Software Requirements:
· Tool:Xilinx vivado/ISE
· Technology: 90nm.
Hardware Requirements:
- Microsoft® Windows XP
- Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
- 512 MB RAM
- 100 MB of available disk space
Learning Outcomes
Learning Outcomes:
· Understanding of low power design principles
· Knowledge of radix-4 prefix tree structure
· Familiarity with hybrid adder designs
· Voltage scaling techniques
· Power optimization techniques
· Communication and presentation skills
· Simulation and analysis
Paper Publishing
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