Low-Power Ternary Multiplication using Approximate Computing

Project Code :TVPGBE128

Abstract

In this paper, a novel approximate computing technique for low-power ternary multiplication is proposed. A carry-truncated ternary multiplier, error compensation circuits and 2×2 ternary multipliers with various accuracies are proposed using the low-power design methodology with Carbon NanoTube FETs (CNTFET). An accuracy-configurable design method is proposed to design energy-efficient 6×6 approximate ternary multipliers. The energy benefit of the proposed 6×6 approximate ternary multipliers has been verified using HSPICE simulation. The proposed approximate design improvement in PDP and accuracy over the previous approximate multiplier-based design.

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Block Diagram

Specifications

Software Requirements:

H-spice
Technology files: 45nm

Hardware Requirements:

Microsoft® Windows XP
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

Introduction to approximate ternary multipliers
Need of ultra-efficient approximate ternary multiplier designs.
Transistors & its applications

Types of Transistors
Logic Gates using Transistors
Pull Up and Pull Down networks
Importance of Transistors

MOS Fundamentals
NMOS/PMOS/CMOS Technologies
How to design circuits using Transistor logic?
Transistor level design for approximate ultra-efficient approximate ternary multiplier
How to design low power, high speed area efficient transistor level circuits?
Drawbacks in CMOS technology
Scope of approximate ternary multiplier in today’s world
Applications in real time
H-Spice tool for design and simulation
Solution providing for real time problems
Project Development Skills: