Low-Power Split-Radix FFT Processors using Radix-2 Butterfly Units
Also Available Domains DSP Core|Cadence EDA
Abstract
Split-radix fast Fourier transform (SRFFT) is an ideal candidate for a low-power FFT processor as it has the lowest number of arithmetic operations among all FFT algorithms. An efficient FFT data addressing scheme as well as twiddle factors are required in the design of such processors. SRFFT's signal flow graph is the same as radix-2 FFT, so conventional FFT data generation address schemes could be applied to SRFFT as well. However, SRFFT has irregular twiddle factor locations and prohibits the use of methods for the generation of radix-2 addresses. This brief presents an architecture of a low-power shared memory SRFFT processor. We demonstrate that a revised radix-2 butterfly unit can be used to measure SRFFT. Multiplier-gating strategy is used by the butterfly system to save dynamic power at the expense of using more hardware resources. Furthermore, two new algorithms for the generation of addresses are developed for both the trivial and nontrivial twiddle factors.
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Block Diagram
Specifications
Software Requirements:
· Xilinx ISE/Vivado , modelsim
Hardware Requirements:
· Microsoft® Windows XP
· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
· 512 MB RAM
· 100 MB of available disk space
Learning Outcomes
- Basics of Digital Electronics
- VLSI design Flow
- Introduction to FFT
- Writing Verilog code.
- Introduction to Radix-2 FFT.
- Knowledge on FFT algorithm.
- Applications in real time
· Xilinx tool for writing code, synthesis and simulation
· Solution providing for real time problems
· Project Development Skills:
o Problem Analysis Skills
o Problem Solving Skills
o Logical Skills
o Designing Skills
o Testing Skills
o Debugging Skills
o Presentation Skills
o Thesis Writing Skills
Paper Publishing
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