Low-Power, Low-Noise Edge-Race Comparator for SAR ADCs

Also Available Domains Low Power VLSI|Cadence EDA

Project Code :TVPGTO10

Objective

The main objective of this work is to reduce the power for Edge race comparator in ADC. The ERC is designed with inverters and NAND gates. The EPC has a longer comparison time and thus it performs noise averaging over a longer time.

Abstract

In this project, a novel voltage comparator, termed an Edge-Race Comparator (ERC), is proposed. It compares the differential input voltage by generating two propagating edges in two inverter loops and by measuring the distance between the two edges. The two edges race with each other and the winner is finally determined.

It can automatically adjust its noise, power consumption, and delay according to the input voltage, thereby saving significant energy and time in coarse comparisons and reducing the noise in fine comparisons (noise averaging is performed over a longer time in fine comparisons). It is well suited for low power, high-resolution Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs) (SAR ADCs). When compared to conventional EPC the proposed EPC shows better results in terms of power. The Proposed Edge-Race Comparator designs implemented using 180nm in Tanner EDA tool.

Keywords: Edge-Race Comparator (ERC), Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) (SAR ADC).

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

Tanner EDA
Technology files:180nm

Hardware Requirements:

Microsoft® Windows XP
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

Introduction to Edge race comparators
Transistors & its applications

Types of Transistors
Logic Gates using Transistors
Pull Up and Pull Down networks
Importance of Transistors

MOS Fundamentals
NMOS/PMOS/CMOS Technologies
How to design circuits using Transistor logic?
Transistor level design for edge race comparators
How to design low power, high speed area efficient transistor level circuits?
Scope of Edge race comparators in today’s world
Applications in real time
Tanner EDA tool for design and simulation
Solution providing for real time problems
Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation Skills
Thesis Writing Skills

Demo Video

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Front End Domains

DSP Core
Communications and Crypto Core
Design for Testability
Arithmetic Core
Nano Technology

Back End Domains

Nano Technology
Core Memories
Transistor Logic
Low Power VLSI

Tools

Cadence EDA
Xilinx Vivado
Xilinx ISE
Tanner EDA
FPGA

Others

Matlab Interfacing