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This project presents a low-power hybrid full adder design using an MGDI-based XNOR gate with a swing restoration technique. The proposed architecture focuses on reducing power consumption and propagation delay while maintaining full voltage swing at the outputs. By employing Modified Gate Diffusion Input (MGDI) logic for the XNOR operation and incorporating swing restoration transistors, the design overcomes threshold voltage loss commonly observed in pass-transistor-based adders
This project presents a low-power hybrid full adder design using an MGDI-based XNOR gate with a swing restoration technique. The proposed architecture focuses on reducing power consumption and propagation delay while maintaining full voltage swing at the outputs. By employing Modified Gate Diffusion Input (MGDI) logic for the XNOR operation and incorporating swing restoration transistors, the design overcomes threshold voltage loss commonly observed in pass-transistor-based adders. Simulation results show that the proposed full adder achieves lower power dissipation, reduced delay, and improved power–delay product (PDP) compared to conventional CMOS and hybrid full adder designs. Due to its energy-efficient operation and reliable output performance, the proposed design is well suited for low-voltage and high-performance VLSI applications.
KEYWORDS: FA (Full adder), CMOS, MGDI (Modified Gate Diffusion Input), VLSI, transmission gate (TG).
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

· Tool Used: Tanner EDA tools for schematic and simulation
· Technology Node: 250 CMOS process.
· Counter Width: 7-bit
· Design Elements: XNOR-XNOR BLOCK, SUM BLOCK , CARRY BLOCK
· Optimization Goal: Reduce power and area while maintaining full-swing outputs and low delay in MGDI-based hybrid full adder design.
Understanding of MGDI logic and its advantages in low-power design
· Knowledge of XNOR-based full adder architectures
· Ability to analyze swing restoration techniques
· Experience in low-power VLSI arithmetic circuit design
· Insight into power, delay, and area trade-offs in hybrid logic circuits