Low Power High Performance 4-bit Vedic Multiplier in 32nm
Also Available Domains Low Power VLSI|Tanner EDA
Abstract
In this paper, a 4 bit Vedic multiplier is designed. The performance of the system basically works better if the performance of the multiplier is good. In today's digital time, Multiplier is one which consumes power at the same time speed of multiplier is playing very important aspects in this. Multiplier Optimization for power and delay both will play an important role. Adders such as Ripple carry adder and carry look-ahead adder and carry skip adder are also having a role in the selection of adder units in the multiplier. Here all the three adders are designed using transmission gates and compared using CMOS.
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Block Diagram
Specifications
Software Requirements:
- Cadence Virtuoso
- Technology files: 45nm
Hardware Requirements:
- Microsoft® Windows XP
- Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
- 512 MB RAM
- 100 MB of available disk space
Learning Outcomes
- Introduction to adders & multipliers
- Types of adders & multipliers
- Need of Multipliers in Dsp applications
- Transistors & its applications
- Types of Transistors
- Logic Gates using Transistors
- Pull Up and Pull Down networks
- Importance of Transistors
- MOS Fundamentals
- NMOS/PMOS/CMOS Technologies
- How to design circuits using Transistor logic?
- Transistor level design for Multipliers
- How to design low power, high speed area efficient transistor level circuits?
- Drawbacks in CMOS technology
- Scope of multipliers in today’s world
- Applications in real time
- Cadence Virtuoso tool for design and simulation
- Solution providing for real time problems
- Project Development Skills:
- Problem Analysis Skills
- Problem Solving Skills
- Logical Skills
- Designing Skills
- Testing Skills
- Debugging Skills
- Presentation skills
- Thesis Writing Skills
Related Projects
Paper Publishing
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