Low Power Digital Circuits Design using 120nm Technology
Also Available Domains Tanner EDA|Cadence EDA
Objective
The main aim of this work is to reduce the power consumption in the digital circuits. The proposed arithmetic circuits were designed with the hybridization of adiabatic and approximate computing, to form a novel family of adiabatic approximate arithmetic circuits
Abstract
In this project, basic logic gates such as AND, OR, XOR using GDI (Gate Diffusion Input) for low power digital circuit design is proposed. With rapid development of portable digital applications, the demand for increasing speed, compact implementation and low power dissipation triggers numerous research efforts. Previously, to improve the performance of logic circuits, traditional CMOS technology is used.
Recently a lot of research has been carried out to design low power, area efficient and high speed designs. This proposed technique allows minimization of power consumption and area. Both layouts and schematic designs are implemented using Cadence tool.
Keywords: Low Power, Area, GDI, CMOS, Logic Gates.
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Specifications
Software Requirements:
- Tanner EDA/ Cadence Virtuoso
- Technology files:180nm
Hardware Requirements:
- Microsoft® Windows XP
- Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
- 512 MB RAM
- 100 MB of available disk space
Learning Outcomes
- Introduction to CMOS & GDI techniques
- Transistors & its applications
- Types of Transistors
- Logic Gates using Transistors
- Pull Up and Pull Down networks
- Importance of Transistors
- MOS Fundamentals
- NMOS/PMOS/CMOS Technologies
- How to design circuits using Transistor logic?
- Low power techniques
- Knowledge on GDI for implementing transistor level design
- How to design low power, high speed area efficient transistor level circuits?
- Scope of GDI in today’s world
- Applications in real time
- Tanner EDA/ Cadence EDA for design and simulation
- Solution providing for real time problems
- Project Development Skills:
- Problem Analysis Skills
- Problem Solving Skills
- Logical Skills
- Designing Skills
- Testing Skills
- Debugging Skills
- Presentation Skills
- Thesis Writing Skills
Paper Publishing
Request Call Back
Would you like to receive a free callback now?
Choose the best time for callback:
Leave your message and we will contact you as soon as possible
6-2-85/B, Old Maternity Hospital Road, Thyagaraja Nagar, Tirupati, Andhra Pradesh – 517501
+91 9030333433
+91 9393939065
0877-2261612
Disclaimer - Takeoff Edu Group Projects are not associated or affiliated with IEEE in any way. The IEEE Projects mentioned here are mentioned in the context of student projects, whose ideas are derived from IEEE publications, not projects of or by IEEE.
