Also Available Domains Low Power VLSI|Tanner EDA
The main aim of this work is to reduce the power consumption in the digital circuits. The proposed arithmetic circuits were designed with the hybridization of adiabatic and approximate computing, to form a novel family of adiabatic approximate arithmetic circuits
In this project, basic logic gates such as AND, OR, XOR using GDI (Gate Diffusion Input) for low power digital circuit design is proposed. With rapid development of portable digital applications, the demand for increasing speed, compact implementation and low power dissipation triggers numerous research efforts.
Previously, to improve the performance of logic circuits, traditional CMOS technology is used. Recently a lot of research has been carried out to design low power, area efficient and high speed designs. This proposed technique allows minimization of power consumption and area. Both layouts and schematic designs are implemented using Cadence tool.
Keywords: Low Power, Area, GDI, CMOS, Logic Gates.
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