Low Power Design of 4-bit Simultaneous Counter using Digital Switching Circuits for Low Range Counting Applications

Also Available Domains Low Power VLSI|Cadence EDA

Project Code :TVPGTO01

Objective

The main objective of this paper is to reduce the power consumption in the counter and it is minimized by using the proposed T Flip-Flop with clock gating technique

Abstract

In this project, True Single Phase Clock Logic (TSPCL) Flipflop with Self-controllable Voltage Level (SVL) technique is proposed to design a 4 bit counter. To minimize the consumption of power, chip area and to enhance the battery life and performance of the system, the low power VLSI circuit is designed.

The major problem in scaling circuit is the power consumption due to the power dissipation in the clock, during standby mode. One-third of the total power is consumed by the clock signal in a counter. The proposed TSPCL with SVL consumes less power compared to conventional TSPCL Flipflop. All the designs are implemented using 250nm technology in Tanner EDA tool.

Keywords: Flip-flop, Low power, SVL, TSPCL.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

Tanner EDA
Technology files:250nm

Hardware Requirements:

Microsoft® Windows XP
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

Introduction to Counters
Transistors & its applications

Types of Transistors
Logic Gates using Transistors
Pull Up and Pull Down networks
Importance of Transistors

MOS Fundamentals
NMOS/PMOS/CMOS Technologies
How to design circuits using Transistor logic?
Low Power technologies
Transistor level design for counters
Importance of static power consumption in lower technology nodes
Techniques for reducing static power consumption
How to design low power, high speed area efficient transistor level circuits?
Scope of Counters in today’s world
Applications in real time
Tanner EDA tool for design and simulation
Solution providing for real time problems
Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation Skills
Thesis Writing Skills

Demo Video

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Front End Domains

DSP Core
Communications and Crypto Core
Design for Testability
Arithmetic Core
Nano Technology

Back End Domains

Nano Technology
Core Memories
Transistor Logic
Low Power VLSI

Tools

Cadence EDA
Xilinx Vivado
Xilinx ISE
Tanner EDA
FPGA

Others

Matlab Interfacing