Low power Dadda multiplier using approximate almost full adder and Majority logic based adder compressors

In Very Large-Scale Integration (VLSI), approximation computing is frequently utilised to create energy-efficient system designs. For signal processing and multimedia applications where low power consumption is the primary consideration, this strategy works best. At the expense of decreased precision, an approximation computation can produce faster and more meaningful results. We presented a number of innovative design strategies in this paper, all based on different monolithic 4:2 compressors. The partial product multiplication process has fewer phases thanks to the proposed approach. Presented Compared to other 4:2 compressors, the monolithic compressor performed better. Our suggested approach uses Dadda multiplication in conjunction with majority logic. This multiplier applies a new-partial product reduction format, lowering the maximum output delay. This strategy considerably lowers the amount of MOSFETs used in comparison to other multipliers, including Wallace Tree Multipliers. Comparisons are made between the simulation results and the traditional Dadda multiplier and ML-based 4:2 compressor.

 INDEX TERMS: —Majority logic, 4:2 compressor, approximate computing, image compression, low power design, Dadda multiplier