Low-Power CMOS Programmable Gain Amplifier with a DC-offset Cancellation for a Direct Conversion Receiver

In modern wireless communication systems, direct conversion receivers (DCRs) offer advantages such as reduced complexity, compact size, and lower cost. However, one of the key challenges in DCR architecture is the presence of DC-offsets that arise from self-mixing and mismatch in the signal path, which can severely degrade performance. This project presents the design and simulation of a low-power CMOS Programmable Gain Amplifier (PGA) with an integrated DC-offset cancellation (DCOC) mechanism, specifically tailored for DCR applications.

The proposed amplifier is designed using CMOS process and optimized for low power consumption while maintaining high linearity and wide programmable gain range. The PGA utilizes a differential architecture to improve common-mode rejection and incorporates digitally controlled gain stages to adjust amplification dynamically based on signal conditions. A feedback-based DC-offset cancellation loop is employed to suppress unwanted DC components without affecting the desired signal.