Low Power Approximate Unsigned Divider Design using Gate Diffusion Input Logic

With the advancement of technology in recent decades and increase of integrated circuits density, the importance of power consumption in design of electronic circuits is steadily increasing. Among the four basic and widely used computational units, division unit has most complexity, so design improvement of this unit has a significant impact on the hardware complexity of the related system. To implement the circuit, GDI is a suitable logic structure to be used. In this structure, the design of complex circuits can be done with less number of transistors and less power consumption. In some applications in digital signal and image processing like machine vision and machine learning, if there are some inaccuracies in calculations, the system still has capability of producing output in an acceptable accuracy range. In this paper, an unsigned approximate division algorithm is proposed and implemented in GDI structure with the aim of reducing the hardware complexity of divider unit. Simulation results reveal that proposed divider implemented in GDI structure compared to its CMOS counterpart show a reduction of 61% in dynamic power consumption, 41% in delay and 69% in area.