Low Power and High-Performance Associative Memory Design

Also Available Domains Cadence EDA|Transistor Logic

Project Code :TVMABE208

Objective

The main objective of this project is to analyze the design a CAM Module using transmission gate logic for various applications.

Abstract

In this project, here designing the CAM cells using NAND Logic, NOR Logic and TG Logic. Standard 6T SRAM cell is used as main building block in this design. This paper reviews Content Addressable Memory (CAM) and its conventional architectures. A model of CAM is proposed using a transmission gate (TG). The new design is proposed with 1-bit storing data. The performance of the proposed design is investigated in terms of the following parameters. power, power delay product (PDP), and transistors count. The design metrics of the circuit are compared at various technology nodes to understand the working better.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

· Tanner EDA

· Technology files: 45nm GPDK

Hardware Requirements:

· Microsoft® Windows XP

· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support

· 512 MB RAM

· 100 MB of available disk space

Learning Outcomes

Introduction to Content addressable Memories
Transistors & its applications

Types of Transistors
Logic Gates using Transistors
Pull Up and Pull Down networks
Importance of Transistors

MOS Fundamentals
NMOS/PMOS/CMOS Technologies
How to design circuits using Transistor logic?
Importance of static power consumption in lower technology nodes
Static power reduction techniques
Transistor level design for TCAMS
How to design low power, high speed area efficient transistor level circuits?
Scope of TCAM in today’s world
Applications in real time
Tanner EDA tool for design and simulation
Solution providing for real time problems
Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation Skills
Thesis Writing Skills

Demo Video

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Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice