Low Latency based Floating Point Multiplier using Parallel Prefix Adders

Floating-point multiplication is a critical operation in high-performance computing, digital signal processing, and scientific applications. Traditional floating-point multipliers often face limitations in latency due to sequential addition stages in the mantissa computation. This paper proposes a low-latency floating-point multiplier architecture that employs parallel prefix adders (PPAs) in the mantissa addition stage. By integrating PPAs, the critical path delay is minimized, resulting in faster computation without compromising precision. The proposed design is implemented and evaluated on FPGA platforms, demonstrating significant improvements in speed and throughput compared to conventional methods. This approach enables high-speed arithmetic operations suitable for real-time and energy-efficient applications