Low-Cost Multiple Bit Upset Correction In SRAM-based FPGA Configuration Frames

Radiation-induced multiple bit upsets (MBUs) are a major reliability concern in Nano scale technology nodes. Occurrence of such errors in the configuration frames of a field programmable gate array (FPGA) device permanently affects the functionality of the mapped design. Periodic configuration scrubbing combined with a low-cost error correction scheme is an efficient approach to avoid such a permanent effect. Existing techniques employ error correction codes with considerably high overhead to mitigate MBUs in configuration frames. In this paper, we present a low-cost error-detection code to detect MBUs in configuration frames as well as a generic scrubbing scheme to reconstruct the erroneous configuration frame based on the concept of erasure codes. The proposed scheme does not require any modification to the FPGA architecture. Implementation of the proposed scheme on a Xilinx Virtex-6 FPGA device shows that the proposed scheme can detect 100% of MBUs in the configuration frames with only 3.3% resource occupation, while the recovery time is comparable with the previous schemes. The effectiveness of the proposed method synthesized and simulated in Xilinx ISE 14.7.