Low-Cost FIR Filter Designs based on Faithfully Rounded Truncated Multiplier Constant Multiplication or Accumulation
Also Available Domains DSP Core|Xilinx Vivado
Abstract
Using the idea of faithfully rounded truncated multipliers, low-cost finite impulse response (FIR) architectures are described. Without compromising the frequency responsiveness and output signal precision, we simultaneously evaluate optimising bit width and hardware resources. It is suggested to reduce the overall area cost by non-uniformly quantizing the coefficients with the appropriate filter order.
An enhanced form of truncated multipliers is used to perform multiple constant multiplication/accumulation in a direct FIR framework. The proposed designs achieve the best area and power outcomes, according on comparisons with earlier FIR design methodologies.
Index Terms—Digital signal processing (DSP), faithful round[1]ing, finite impulse response (FIR) filter, truncated multipliers, VLSI design.NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Block Diagram
Specifications
Software Requirements:
· Xilinx ISE/Vivado
Hardware Requirements:
· Microsoft® Windows XP
· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
· 512 MB RAM
· 100 MB of available disk space
Learning Outcomes
- Basics of Digital Electronics
- VLSI design Flow
- Introduction to Binary FIR filters
- Writing Verilog code.
- Introduction to transposed and direct form FIR filters.
- Knowledge on Rounded Truncated Multiple Constant Multiplication/Accumulation.
- Applications in real time
· Xilinx tool for writing code, synthesis and simulation
· Solution providing for real time problems
· Project Development Skills:
o Problem Analysis Skills
o Problem Solving Skills
o Logical Skills
o Designing Skills
o Testing Skills
o Debugging Skills
o Presentation Skills
o Thesis Writing Skills
Paper Publishing
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