Local Bit-Line SRAM Architecture With Data-Aware Power-Gating Write Assist

This paper introduces a novel SRAM (Static Random-Access Memory) architecture that leverages data-aware power-gating write assist to enhance both energy efficiency and write performance. In an era of ever-increasing data-centric computing demands, the proposed architecture addresses the challenges of power consumption and write latency in on-chip memories.

The key innovation in this architecture lies in its ability to intelligently apply power-gating techniques to SRAM cells based on the data content being written. Traditional power gating typically involves completely isolating SRAM cells from the power supply during idle periods, incurring significant overhead when reactivating cells for write operations. In contrast, our data-aware approach selectively activates SRAM cells, reducing the overhead associated with write assist techniques.