LFSR-Reseeding Scheme for Achieving Test Coverage
Also Available Domains Design for Testability|Xilinx Vivado
Objective
To improve encoding performance, it additionally uses LFSR reseeding to lower the amount of specified bits.
Abstract
Power dissipation during testing has become a major issue as the size and complexity of systems-on-chips continue to increase. The flip-flops undergo more transitions during scan shifting than they do during regular functional operation. The test power and test storage can be greatly reduced by combining the suggested encoding approach with a partial LFSR reseeding scheme. Following LFSR reseeding, the encoding scheme serves as the second stage of compression. By using alternative methods to fill the number of undetermined bits, the number of transitions in the scan chain can be decreased. To improve encoding performance, it additionally uses LFSR reseeding to lower the amount of specified bits. The non-transitional blocks' set amount of bits can be decreased, and this procedure can stop all transitions in such blocks.
Keywords – Test data compression, Linear Feedback Shift Register (LFSR), Reseeding, Test power
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Specifications
Software Requirements:
· Xilinx ISE/Vivado
Hardware Requirements:
· Microsoft® Windows XP
· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
· 512 MB RAM
· 100 MB of available disk space
Learning Outcomes
- Basics of Digital Electronics
- VLSI design Flow
- Introduction to LFSR
- Writing Verilog code.
- Introduction to LFSR Reseeding scheme
- Knowledge on Encoding scheme.
- Applications in real time
· Xilinx tool for writing code, synthesis and simulation
· Solution providing for real time problems
· Project Development Skills:
o Problem Analysis Skills
o Problem Solving Skills
o Logical Skills
o Designing Skills
o Testing Skills
o Debugging Skills
o Presentation Skills
o Thesis Writing Skills
Paper Publishing
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