Project Code :TVMAFE184
Objective
The main objectives of this project is to design an efficient Traffic Light Controller in order to overcome the problems raised by IA-TLC
Abstract
For the economic development and progress of any country, roads play an important role by providing transportation ease for goods as well as for passengers. The number of vehicles on road is increasing day by day which are controlled by the traditional Traffic Light Controller in the countries like India and other developing countries. In traditional Traffic Light Controller, fied time is allotted for traffic on each road to pass irrespective of the traffic intensity. This is an inefficient controlling method which consumes time, effort and fuel of users unnecessarily; also it doesn't have any provision of sensing and giving priority for the emergency vehicles to pass fist. This problem is addressed by using Intelligent and Adaptive Traffic Light Controller (IA-TLC) implemented on FPGA using Verilog as an example of FSM with 35 states. FPGA, microcontroller and ASIC designs have been used for traffic light controller. Reason for selecting FPGA is that it has numerous merits over microcontroller in TLC design. Some of these merits are high speed of operation, more number of input/output ports and better performance 111. In IA-TLC density of traffic is sensed by using IR sensors throughout day and night, and accordingly time is allotted for users to pass. Other advantages of this system are: i) System senses emergency vehicles on the individual road moreover it gives priority to the traffic of that particular road where the emergency vehicles is sensed. ii) Finds out defaulter who crosses the red signal by capturing images using camera. The design is simulated, synthesized and power estimation was done using Xilinx 14.3.
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Specifications
Hardware requirement
Processor - Pentium βIII
Speed - 1.1 GHz
RAM - 1 GB (min)
Hard Disk - 40 GB
Floppy
Drive - 1.44 MB
Key Board - Standard Windows Keyboard
Mouse - Two or Three Button Mouse
Monitor - SVGA
Software requirements
- Operating System
:Windows95/98/2000/XP/Windows
- Front End : Modelsim
6.3 for Debugging and Xilinx 14.3 for Synthesis and Hardware Implementation
- This
softwareβs where Verilog source code can be used for design implementation.