Integration of Optimized GDI Logic based NOR Gate and Half Adder into PASTA for Low Power & Low Area Applications

Abstract: The utilization of MOS technology is prevalent in VLSI circuits for reducing the number of transistors and achieving low power consumption. This can be accomplished via either circuit level optimization or logical level optimization. This paper focuses on circuit level optimization to reduce the area and power consumption. A conventional complementary static CMOS (CSCMOS) technology is used to design a parallel self-timed adder circuit where the number of NMOS and PMOS transistors is equal. However, this approach requires a large number of transistors, resulting in high area and power consumption. To address this issue, the proposed parallel asynchronous self-time adder (PASTA) technique utilizes modified gate diffusion input (GDI) logic. Additionally, the structure of the XOR gate and half adder are minimized to achieve low area and low power consumption. A comparison between the two techniques is performed, and the results demonstrate that the proposed GDI logic-based PASTA utilizes fewer transistors (area) and has lower power consumption than the existing CSCMOS technique. The functionality of the PASTA circuits is verified through simulations conducted via the tanner tool.