Input-Conscious Approximate Multiply-Accumulate (MAC) Unit for Energy-Efficiency
Also Available Domains DSP Core|Arithmetic Core|Xilinx Vivado
Objective
The main objective of this project is to implement a MAC architecture with reduced delay. The MAC structure is designed with novel multiplier design and carry save adder.
Abstract
The Multiply-Accumulate Unit (MAC) is an integral computational component of all Digital Signal Processing (DSP) architectures and thus has a significant impact on their speed and power dissipation. Due to an extraordinary explosion in the number of battery-powered ‘‘Internet of Things’’ (IoT) devices, the need for reducing the power consumption of DSP architectures has tremendously increased. In this paper, 4 approximate adder designs are implemented for multipliers design which are used in the proposed mac unit. Simulation results show that the proposed MAC unit has better area and power consumption compared to the existing MAC unit.
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Block Diagram
Specifications
Software Requirements:
- Xilinx ISE Tool
- HDL: Verilog
Hardware Requirements:
- Microsoft® Windows XP
- Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
- 512 MB RAM
- 100 MB of available disk space
Learning Outcomes
- Basics of Digital Electronics
- FPGA design Flow
- Introduction to Verilog Coding
- Different modeling styles in Verilog
- Data Flow modeling
- Structural modeling
- Behavioral modeling
- Mixed level modeling
- Introduction to MAC unit
- About Partial Product Generation
- Knowledge on Adders
- About Registers
- Applications in real time
- Xilinx ISE 14.7 for design and simulation
- Generation of Netlist
- Solution providing for real time problems
- Project Development Skills:
- Problem Analysis Skills
- Problem Solving Skills
- Logical Skills
- Designing Skills
- Testing Skills
- Debugging Skills
- Presentation Skills
- Thesis Writing Skills
Paper Publishing
Request Call Back
Would you like to receive a free callback now?
Choose the best time for callback:
Leave your message and we will contact you as soon as possible
6-2-85/B, Old Maternity Hospital Road, Thyagaraja Nagar, Tirupati, Andhra Pradesh – 517501
+91 9030333433
+91 9393939065
0877-2261612
Disclaimer - Takeoff Edu Group Projects are not associated or affiliated with IEEE in any way. The IEEE Projects mentioned here are mentioned in the context of student projects, whose ideas are derived from IEEE publications, not projects of or by IEEE.
