In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers

In this project, a novel mesochronous Dual-clock Buffer is proposed, where the transmitter and receiver modules at the two ends of a mesochronous interface receive the same clock signal, thus operating under the same clock frequency but have different phase difference. In such cases, clock synchronization is needed when sending data across modules. In this project, we present a novel mesochronous dual-clock first-input– first-output (FIFO) buffer that can handle both clock synchronization and temporary data storage can be achieved. The proposed design can operate correctly even when the transmitter and receiver are separated by a long link whose delay cannot fit within the target operating frequency. In such scenarios, the proposed mesochronous FIFO can be extended to support multi-cycle link delays in a modular manner and with minimal modifications to the baseline architecture.

Keywords: FIFO, Mesochronous FIFO, synchronous FIFO butter