Improvising Data Security using Blow Fish Algorithm

Also Available Domains Arithmetic Core|Xilinx ISE

Project Code :TVMATO684

Objective

The main objective of this paper is to implement the blow fish algorithm for the encryption and decryption of binary data sequence providing the fastest and high encrypted data rate

Abstract

In this paper, information passes across the network by means of various paths. It is essential to provide security for the information in order to control unauthorized access of data in any form. Cryptography is the concept of securing the data by retaining its authenticity and without non-repudiation. Encryption and decryption are the two basic complementary processes which involves in any cryptographic algorithm to protect the data integrity. The data security is ensured by transforming a plain text into unreadable format by encrypting text using cryptographic algorithms. To enhance the data security across the network it is very significant to encode the data in unreadable form. The paper proposes a method to implement digital data sequence in the form of binary data using blow fish algorithm. Here both the concept of binary data of input is encrypted and random values are generated which are encrypted keys of the input message. The receiver will get the encrypted data which is then extracted to get the original message in the form of binary data. In this method both sender and receiver will share a common binary sequence for encryption and decryption process.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

Xilinx Vivado
HDL: Verilog

Hardware Requirements:

Microsoft® Windows XP
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

Basics of Digital Electronics
VLSI design Flow
Introduction to Verilog Coding
Different modeling styles in Verilog

Data Flow modeling
Structural modeling
Behavioral modeling
Mixed level modeling

Introduction to cryptography
About arithmetic circuits
Knowledge on encryption and decryption
Knowledge on cryptography algorithms
About S-box, p-arrays of cryptography algorithms
Applications in real time
Xilinx Vivado for design and simulation
Generation of Netlist
Solution providing for real time problems
Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation Skills
Thesis Writing Skills

Demo Video

Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice