Improvement of Accuracy of Fixed-Width Booth Multipliers using Data Scaling Technology

Also Available Domains Arithmetic Core|Xilinx Vivado

Project Code :TVPGTO369

Objective

The main aim of this work is to reduce the error rate in Booth multiplier by using Data Scaling Technology. The truncation errors in FWBMs are reduced by adding a circuit incorporating the proposed DST to them as well as an error-compensation circuit

Abstract

In this project, we propose a Data Scaling Technology (DST) for use in a low-error Fixed-Width Booth Multiplier (FWBM) to reduce truncation errors. The proposed DST uses the redundant bits of the multiplicand to more efficiently obtain bits for low-error FWBMs.

More specifically, this method reduces the truncated partial products, which are used to estimate the compensation bias; however, the calculations in the FWBM are increased. The accuracy of the FWBM can be improved by adding the proposed DST circuit to it.

These results indicate that the use of the proposed DST increases the accuracy of low-error FWBMs with only a small area overhead. The effectiveness of the proposed method is designed using Xilinx ISE 14.7

Keywords: Fixed-Width Booth multiplier (FWBM), Truncation error, Data Scaling Technology (DST)

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

Xilinx ISE 14.7
HDL: Verilog

Hardware Requirements:

Microsoft® Windows XP
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

Basics of Digital Electronics
FPGA design Flow
Introduction to Verilog Coding
Different modeling styles in Verilog

Data Flow modeling
Structural modeling
Behavioral modeling
Mixed level modeling

Combinational & Sequential circuits
Knowledge on Arithmetic circuits
About Booth multiplier circuit
Data scaling technology
About parallel prefix adders
Applications of multipliers in real time
Xilinx ISE 14.7 for design and simulation
Generation of Netlist
Solution providing for real time problems
Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation Skills
Thesis Writing Skills

Demo Video

Front End Domains

DSP Core
Communications and Crypto Core
Design for Testability
Arithmetic Core
Nano Technology

Back End Domains

Nano Technology
Core Memories
Transistor Logic
Low Power VLSI

Tools

Cadence EDA
Xilinx Vivado
Xilinx ISE
Tanner EDA
FPGA

Others

Matlab Interfacing