Implementation of Turbo Encoder and Decoder
Also Available Domains Xilinx Vivado|Xilinx ISE
Objective
Turbo code has become the coding technique of choice in many communication and storage systems due to its near Shannon limit error correction capability. With requirement on increasing data rates for deep space mission, it is required to have efficient encoder and decoder.
Abstract
Turbo code has become the coding technique of choice in many communication and storage systems due to its near Shannon limit error correction capability. With requirement on increasing data rates for deep space mission, it is required to have efficient encoder and decoder. Turbo codes provide up to 0.8 dB improvement in Eb/No over the current best codes used by deep space missions. The total number of decoder iterations depends on the physical channel characteristics. In this paper, we proposed a turbo encoder with the 1/3,1/4,1/6 rate and turbo decoder.
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Block Diagram
Specifications
Software Requirements:
· Tool: Xilinx ISE 14.7 /Xilinx Vivado2018.3
· HDL: Verilog
Hardware Requirements:
· Microsoft® Windows XP
· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
· 512 MB RAM
· 100 MB of available disk space
Learning Outcomes
- Basics of Digital Electronics
- VLSI design Flow
- Introduction to Verilog Coding
- Different modeling styles in Verilog
o Data Flow modeling
o Structural modeling
o Behavioral modeling
o Mixed level modeling
- Introduction to turbo encoder and decoder
- Knowledge on TURBO architecture
- Different instruction sets
- Knowledge on ENCODER AND DECODER
- Applications in real time
- Xilinx ISE 14.7/Xilinx Vivado2018.3 for design and simulation
- Generation of Netlist
- Solution providing for real time problems
- Project Development Skills:
o Problem Analysis Skills
o Problem Solving Skills
o Logical Skills
o Designing Skills
o Testing Skills
o Debugging Skills
o Presentation Skills
o Thesis Writing Skills
Related Projects
Paper Publishing
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